SizeAgent

Transistor sizing of a SKY130 two-stage Miller op-amp, treated as a combinatorial optimization problem. Five search strategies and a tool-calling LLM agent compete on the same budget of real ngspice simulations, and the winners are checked across PVT corners and Monte Carlo mismatch.

Source on GitHub Try the surrogate model Agent trace

The problem

SkyWater SKY130 transistor models are binned. Each device group can only use a characterized (W, L) per finger, times an integer multiplier. Together with grids for Cc, Rz and the bias current, that makes a discrete search space of sizings. A design meets spec only if every one of these targets is met at once:

VDD 1.8 V M3/M4 PMOS loadgroup load · m3 M1/M2 NMOS pairgroup inp · m1 M5 tail · M8 biasgroup bias · m5 M6 PMOS 2nd stagegroup cs · m6 M7 current sinkgroup bias · m7 out1 Rz + Cc (Miller)out → CL 2 pF
How each run works
  1. An optimizer or the agent proposes a sizing from the discrete space.
  2. ngspice runs an open-loop AC testbench. A 1 GH inductor closes the loop at DC to set the bias point.
  3. Gain, UGBW, phase margin, power, saturation margin of every transistor, and DC offset are measured.
  4. A normalized spec violation is scored. Feasible designs are then ranked by power.
  5. Each strategy gets the same SPICE budget, and repeated designs are cached and not counted.

Benchmark: simulations needed to meet spec

Median best cost so far over seeds, with the interquartile band shaded. Values below 1.0 mean every spec is met. Lower is better.

*Median over all seeds. A run that never met spec counts as worse than the budget, so the median reads ">300" when fewer than half the runs succeeded.

LLM agent trace

The agent reads operating points (gm/ID, overdrive, saturation margin) and reasons from first-order design equations. It can hand off to a short simulated-annealing local search (refine) and check PVT corners before it submits.

Surrogate vs. SPICE

A PyTorch MLP ensemble trained on SPICE results, scored on held-out designs. Inside the surrogate-assisted GA, the same kind of model screens 400 offspring per generation and only the most promising 10 go to SPICE.

Try it: live surrogate prediction

Pick a sizing and the trained ensemble predicts its performance in your browser. These are model predictions, not SPICE results, so check the R² values above before trusting them.

Power uses the ideal-mirror estimate P = VDD · Ib · (1 + m5 + m7), which runs a few percent above SPICE because of channel-length modulation. Everything else is predicted by the model. Reality check: for the default sizing loaded here, SPICE gives 75.3 dB gain, 40.7 MHz UGBW, 60.2° phase margin, 228 µW, a 32 mV saturation margin and a 1.8 mV offset. Comparing those numbers with the predictions shows the size of the model error.

Robustness: PVT corners and Monte Carlo

The best design from each optimizer is re-simulated at 5 process corners (tt, ff, ss, fs, sf) × 3 temperatures (−40, 27, 125 °C), plus 100 mismatch Monte Carlo runs. These designs were optimized at nominal conditions only, so this table shows how much margin each one kept.